The present invention relates to variable capacitors, specifically to p-n junction reverse bias voltage controlled capacitors.
Variable capacitors are used in many applications, including high frequency applications to tune oscillators, mixing circuits, multipliers, analog and digital phase shifter circuits, and for impedance matching and control in microwave IC applications. Voltage controlled capacitors (VCCs) are usually formed using reverse biased p-n junctions. The junction capacitance depends on the applied voltage and the design of the junction, including whether the junction is abrupt or graded. Carrier concentration difference between the p and n regions causes diffusion. This diffusion creates charge imbalance, which produces an electric field that tends to counteract the diffusion. In thermal equilibrium, the net flow of carriers is zero. The space charge region near the junction where mobile carrier concentrations have been reduced to below thermal equilibrium value is called the depletion or space charge region.
In typical voltage controlled capacitors the diodes are contained within well regions. FIG. 1 shows such capacitor. A positively doped region 102 exists within an n well region 104, which creates a diffusion layer 106 (the space charge region) between them. The depletion region is not planar in such a capacitor because of the configuration of the n and p regions. A built-in potential, Vbi, exists across the depletion region 106. This potential depends on the acceptor and donor impurity concentrations according to the following expression.       V    bi    =            Kt      q        ⁢          ln      ⁢              (                                            N              A                        ⁢                          N              D                                            n            i            2                          )            
The width of the depletion region, WSCR, depends on the built-in potential and varies with the applied voltage. WSCR is given by the following expression.       W    SCR    =            (                        2          ⁢                      K            s                    ⁢                                    ε              0                        ⁢                          (                                                V                  bi                                -                                  V                  App                                            )                                ⁢                      (                                          N                A                            +                              N                D                                      )                                    q          ⁢                      (                                          N                A                            ⁢                              N                D                                      )                              )              1      /      2      
The width of the depletion region width also determines the junction capacitance.       C    J    =                    K        s            ⁢              ε        0            ⁢      A              W      SCR      
In these expressions, T is temperature, Ks is the relative dielectric constant of the semiconductor (1.18 for silicon), epsilon naught is 8.854xc3x971031 14 farad/cm, k is Boltzmann""s constant, ni is the intrinsic carrier concentration, NA is the acceptor impurity concentration, ND is the donor impurity concentration, and VAPP is the applied voltage. FIG. 1 also shows P+ and N+ implants 108, 110 which serve as low resistance contacts.
Capacitive coupling between the well and the substrate and other stray capacitances cause parasitic capacitance in most VCCs. Parasitic capacitance limits high frequency operation and causes RF (radio-frequency) energy loss to the substrate. Triple well processes can eliminate some of these problems. However, in a triple well process the VCC parasitic capacitance to the well may change with bias since the depletion region is sensitive to total bias. This leads to added non-ideal VCC behavior. Also, three-terminal bias techniques are required to minimize capacitive coupling. Further, triple well processes add complexity and high cost to a bulk silicon process.
Some VCCs require the use of polysilicon VCC diodes for isolation improvement which usually have higher resistance and nonlinear behavior due to grain boundaries in the polysilicon.
It is therefore desirable to have a VCC circuit that has minima parasitic capacitance and resistance, more linear behavior than previous polysilicon diode capacitors, and that is easy to implement into standard processes.
Improved RF Voltage Controlled Capacitor on Thick-Film SOI
The present application discloses a VCC built within the thin film region between a buried oxide (BOX) and a shallow trench. This forms a near ideal diode with minimal parasitic capacitance and resistance.
In one class of embodiments, the VCC is formed on an integrated circuit using the SOI layer already present in a standard BiCMOS process. In the preferred embodiment, a PBL (p-doped buried layer) and an NBL (n-doped buried layer) form the lateral contacts of the VCC. The SOI layer is bounded on the bottom by a buried oxide layer. Shallow trench isolation covers the top of the active region of the VCC. Deep trench isolation bounds the contact regions and also bounds the active edge regions of the VCC for maximum device isolation.
Alternative embodiments include using n-well or p-well implants to form one or both ends of the diode instead of a buried layer. This minimizes the required area for the VCC. The doping of the VCC active region can be varied as well. For instance, the intrinsic doping of the thin film region can be used, or an additional mask step can be added to ion implant n-type or p-type dopants into the active region. Because of the lateral design of this VCC, a simple change in device layout allows the design of high voltage VCC structures with no changes in process. This is not obtainable for VCC designs using vertical device structures.
Though the preferred embodiment uses a P+ to n-well diode to form the capacitor, the innovations of the present application apply equally to N+ to p-well diodes for the VCC.
The presently disclosed teachings are also applicable to a VCC with an abrupt junction, or with graded junctions of various types within the diode.
The disclosed innovations, in various embodiments, provide one or more of at least the following advantages:
low parasitic capacitance;
low resistance;
implementation into existing standard processes;
linear voltage control response.